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Dépôt Institutionnel de l'Université Ferhat ABBAS - Sétif 1 >
Faculté de Technologie >
Département d'Electronique >
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| Titre: | Optimized FPGA Implementation of round-based ciphers : a high-performance and area-efficient AES implementation |
| Auteur(s): | Kerbouche, Abdelaziz |
| Mots-clés: | Advanced Encryption Standard (AES) algorithm
Field Programmable Gate Array (FPGA) |
| Date de publication: | 30-oct-2025 |
| Résumé: | This project aims to identify an optimal implementation technique for security algorithms in embedded systems, balancing resource utilization and timing performance. The primary challenge addressed is maintaining the integrity of the security algorithm while optimizing hardware architecture to maximize efficiency. The Rijndael algorithm, specifically the Advanced Encryption Standard (AES), is chosen as the security core and implemented using two distinct techniques. The proposed approach is designed for FieldProgrammable Gate Arrays (FPGAs), with results benchmarked against similar projects in terms of timing and area performance |
| URI/URL: | http://dspace.univ-setif.dz:8888/jspui/handle/123456789/6212 |
| Collection(s) : | Thèses de doctorat
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